1. Field of the Invention
The present invention relates generally to sense amplifiers, and more particularly to complementary metal-oxide-silicon field effect transistor (CMOS-FET) sense amplifiers for readout of dynamic random access memory (DRAM) integrated circuit structures.
2. Background Art
The prior art contains many references describing various memory-array sense amplifiers using complementary metal oxide semiconductor devices such as field effect transistors (CMOS-FETs).
Examples of such references are provided in the following patents.
U.S. Pat. No. 4,169,233 issued Sept. 25, 1979 to Haraszti, entitled High Performance CMOS Amplifier, describes a sense amplifier circuit fabricated from complementary metal oxide semiconductor field effect transistors (CMOS-FETs) for applications in a radiation hardened environment. The sense amplifier is characterized by high sensitivity, high gain, good noise immunity, low power dissipation, fast operation, relatively small geometrical size, and good stabilization for temperature and supply effects while providing self-compensation for non-uniformities of electrical parameters which may occur as the result of MOS device processing or exposure to a nuclear radiation event. The sense amplifier circuit of FIG. 6 of the patent includes added transistors Q27 and Q29, but for purposes distinct from the present invention.
U.S. Pat. No. 4,375,600 issued Mar. 1, 1983 to Wu, entitled Sense Amplifier For Memory Array, describes a memory-array sense amplifier that includes a grounded-gate depletion-mode FET connected between a bitline and a sense node. Another FET connects a supply voltage VDD to the sense node when turned on by a clock phase signal. Further FETs form a latch circuit.
U.S. Pat. No. 4,262,341 issued Apr. 14, 1981 to Mogi et al, entitled Memory Circuit, relates to the addition of a capacitor circuit for augmenting the voltages at predetermined points in a sense amplifying circuit, in order to ensure a satisfactory refreshing of memory cells, since, if the potentials at the connecting points between a sense amplifying circuit and bitlines fall below a predetermined value when the sense amplifying circuit is caused to operate, it is difficult to achieve a complete refreshing of the memory cells. Transistors Q1 and Q2 can disconnect the bitlines from being discharged during development of sensed value in transistors Q3 and Q4.
U.S. Pat. No. 4,069,474 issued Jan. 17, 1978 to Boettcher et al, entitld MOS Random Acces Memory Having an Improved Sensing Circuit, discloses a memory circuit wherein first and second bitline portions, each having a plurality of memory cells coupled thereto are provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifier is coupled between the first and second bit portion for sensing the voltage difference therebetween and for latching into one of the two states in response to sensing either a "0" or a "1" accessed to one of the bitline portions from an addressed memory cell to be read out of the memory.
In U.S. Pat. No. 4,236,231 issued Nov. 25, 1980 to Taylor and entitled Programmable Threshold Switchable Resistive Memory Cell Array, a memory-array is described wherein each memory cell includes a pair of threshold resistive elements which switch from a high to low resistance state when a potential above their respective programmable thresholds is applied. A binary value is stored by creating a threshold difference between the two resistive elements using two different value current sources. The binary value stored is read by applying a ramp potential and determining which threshold resistive element switched states first using a sense latch.
U.S. Pat. No. 4,247,791 issued Jan. 27, 1981 to Rovell, entitled CMOS Memory Sense Amplifier, discloses a complementary metal oxide semiconductor (CMOS) field effect transistor (FET) memory sense amplifier to detect a relatively small differential voltage that is superimposed on a relatively large common mode precharge signal. The sense amplifier is implemented so as to provide latched output signals after a short time delay and in response to sensed input signals that are supplied via a pair of data bus lines.
U.S. Pat. No. 4,354,257 issued Oct. 12, 1982 to Varshney et al, entitled Sense Amplifier for CCD Memory, describes a snese amplifier for use with a charge coupled device in which capacitive coupled charge is employed with a flip-flop circuit to accelerate sense and readout. Operation of the amplifier is effected with two external clocks and two internally generated clocks.
U.S. Pat. No. 4,421,996 issued Dec. 20, 1983 to Chuang et al, entitled Sense Amplification Scheme for Random Access Memory, describes a source-clocked type of cross-coupled latch sense amplifier of a dynamic random access memory device including a sense clock that employs multiple extended dummy memory cells to provide reference timing which tracks time constants of word line, cell transfer gate, cell capacitor,and bitline, and the sense clock is further compensated over large variations of fabrication process parameters and operating conditions. The trigger and slave clock circuit are chained in series to control the timing sequence of a plurality of clocked output signals. The clocked output signals are selectively amplified and summed in parallel to generate current with an intended dynamic characteristic. The current so generated is applied to the common source electrodes of the cross-coupled latch.
In U.S. Pat. No. 3,949,381 issued Apr. 6, 1976 to Dennard et al, entitled Differential Charge Transfer Sense Amplifier, a differential charge transfer amplifier, which functions as a sensing and regenerating circuit responsive to binary information represented by the level of charge in a stored charge memory cell is disclosed.
U.S. Pat. No. 3,879,621 issued Apr. 18, 1973 to Cavaliere et al, entitled Sense Amplifier, discloses an FET sense amplifier for converting a double rail differential memory output signal to a full logic output signal, the amplifier comprising first and second pairs of FETs coupled together at a pair of common nodes. In one embodiment, first and second field effect transistors of the same conductive type are connected to respective ones of the nodes. A third field effect transistor of a second conductive type is connected to one of the pairs of FETs, the first, second and third field effect transistors are interconnected so that when the first and second transistors conduct the third transistor is cut off, and when the first and second transistors are cut off, the third transistor conducts.
U.S. Pat. No. 3,671,772 issued June 20, 1972 to Henle, entitled Difference Amplifier, disposes a difference amplifier used as a sense amplifier for stored binary data being read from a computer memory. The amplifier includes a pair of cross-coupled transistors, a power source providing an operating voltage for said transistors, and means for intermittently applying said power source to the cross-coupled transistors. Selective application means apply each of the pair of voltage signals to be differentiated from each other to a respective one of the pair of cross-couplings, i.e., the pair of cross-connected regions in the transistors. In the case of reading from binary storage, the voltage signals are applied from the pair of sense lines from the memory storage. The signals are applied during a period when the voltage source is not being applied and, consequently, both of the paired transistors are in the non-conductive state. The signals establish a stored charge in each of the transistors; the difference between these charges will determine which of the transistors assumes the conductive state when the power is subsequently applied.
U.S. Pat. No. 3,648,071 issued Mar. 7, 1972 to Mrazek, entitled High-Speed MOS Sense Amplifier, relates to an improved sense amplifier comprised of an all FET amplifying circuit having means for limiting the voltage swing of the read potential applied thereby to an integrated circuit memory array in sensing the stored "1" and "0" memory states. The amplifier includes upper and lower output level-limiting circuits which detect predetermined signal levels in the output signal of the amplifier and cause the impedences at the input of the amplifier to be adjusted to limit the output signal swing of the amplifier to within the predetermined signal leads. In so doing, the memory read potential is also constrained to swing within certain predetermined limits.
U.S. Pat. No. 3,560,765 issued Feb. 2, 1971 to Kubinec, entitled High Speed MOS Read-Only Memory, describes a sense-amplifier for use with a read-only memory apparatus and having menas for limiting to less than six volts, the voltage to which the memory elements are subjected. An all FET amplifier structure is provided having an input stage which clamps the output voltage of the memory device to a predetermined potential and presents the output of the memory from causing this potential to swing more than a predetermined value when a storage element is gated ON.
U.S. Pat. No. 4,053,873 issued Oct. 11, 1977 to Freeman et al, entitled Self-Isolating Cross-Coupled Sense Amplifier Latch Circuit, discloses a self-isolating cross-coupled sense amplifier latch circuit having five enhancement mode field effect transistor devices and two depletion mode field effect transistor devices. The first and second field effect transistors form a cross-coupled pair with true and complement outputs being available at the cross-coupled nodes. A third field effect transistor is connected to a common connection between the source electrodes of the cross-coupled pair and is used to establish a race condition after a small difference in potential has been applied to the aforementioned output nodes. A pair of depletion mode devices are connected as diodes between a positive potential (VH) and each of the output nodes, respectively. Each of the output nodes is connected to a respective bitline of a column of memory cells through enhancement mode field effect transistors connected as third and fourth unidirectionally conducting devices.
U.S. Pat. No. 3,789,312 issued Jan. 29, 1974 to Heller et al, entitled Threshold Independent Linear Amplifier, describes a system wherein low level pulses in the order of 100 millivolts or less can be detected and amplified regardless of variations in the voltage required to turn on the active device used in the amplifier. This is achieved by coupling an active device between a capacitor and a capacitively loaded output line, charging the output line to a reference voltage, applying a level setting voltage to the device to turn on the device; charging the capacitor to a voltage substantially equivalent to the level setting voltage to turn off the device while maintaining it such that any input signal superimposed on the level setting voltage will cause the device to again turn on and discharge the capacitively loaded output line thereby amplifying and inverting the superimposed input signal. The invention is particularly useful for sensing random access integrated semiconductor memories.